Presentation 2001/3/16
Sample Preparation Technique for Failure Analysis.
Shinji Nakamura, Shigeru Nakajima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes a samplep reparation technique to improve the obserbabirity of failure site of device and wire repair technique for LSI design verification. A partial remove of wide upper metal wire, fabrication of inclined grooves that is reflection mirror of light emission, and bacd side preparation for the back-side light emission microscopy are useful techniques for little light emission is detected from front side of device. Anisotropic etching by RIE is also useful for EB probing or multilay er wiring. A cross-sectional TEM preparation using FIB, SEM observation preparation using lapping and selective wet-etching fabrication are very effective technique for micro-structure analysis of minimized and multilayeered LSI and flip-chip packaged device.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) LSI Failure analysis / Back side light emissin microscopy / Reactive ion etching / X-TEM / FIB / EB testing
Paper # R2000-48,CPM2000-171
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Conference Information
Committee CPM
Conference Date 2001/3/16(1days)
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Paper Information
Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Sample Preparation Technique for Failure Analysis.
Sub Title (in English)
Keyword(1) LSI Failure analysis
Keyword(2) Back side light emissin microscopy
Keyword(3) Reactive ion etching
Keyword(4) X-TEM
Keyword(5) FIB
Keyword(6) EB testing
1st Author's Name Shinji Nakamura
1st Author's Affiliation NTT Electronics Corporation()
2nd Author's Name Shigeru Nakajima
2nd Author's Affiliation NTT Electronics Corporation
Date 2001/3/16
Paper # R2000-48,CPM2000-171
Volume (vol) vol.100
Number (no) 707
Page pp.pp.-
#Pages 6
Date of Issue