| Presentation | 2000/12/1 Introducing a new method that successively extracts circuit from CAD layout to the CAD navigation and its application to failure analysis of system LSIs K. Norimatsu, T. Miyazaki, J. Kinashi, A. Matsuo, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In failure analysis, CAD navigation method with cross mapping capability is indispensable for failure analysis engineers that are not familiar with the inside of the design. But, in actual cases, it is often hard to obtain the complete cross mapping data of the designs with shorter time and it prevents us from setting about the failure analysis soon. In these cases, this method that successively extracts circuit from CAD layout data is very useful for obtaining necessary cross mapping information. In this paper we describe the necessity of this method and show some examples of its application to the failure analysis of system LSIs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CAD navigation / CAD layout data / successive circuit extraction / turn around time / layout versus schematic |
| Paper # | CPM2000-145,ICD2000-178 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2000/12/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Introducing a new method that successively extracts circuit from CAD layout to the CAD navigation and its application to failure analysis of system LSIs |
| Sub Title (in English) | |
| Keyword(1) | CAD navigation |
| Keyword(2) | CAD layout data |
| Keyword(3) | successive circuit extraction |
| Keyword(4) | turn around time |
| Keyword(5) | layout versus schematic |
| 1st Author's Name | K. Norimatsu |
| 1st Author's Affiliation | Packaging & Test Engineering Dept., System LSI Div., Semiconductor Company, Toshiba Corporation() |
| 2nd Author's Name | T. Miyazaki |
| 2nd Author's Affiliation | Packaging & Test Engineering Dept., System LSI Div., Semiconductor Company, Toshiba Corporation |
| 3rd Author's Name | J. Kinashi |
| 3rd Author's Affiliation | Test System Development Dept., Toshiba Microelectronics Corporation |
| 4th Author's Name | A. Matsuo |
| 4th Author's Affiliation | Test System Development Dept., Toshiba Microelectronics Corporation |
| Date | 2000/12/1 |
| Paper # | CPM2000-145,ICD2000-178 |
| Volume (vol) | vol.100 |
| Number (no) | 486 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |