Presentation 2000/12/1
Layout Design for LSI Circuit Modification
Norio KUJI, Tadao TAKEDA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Novel LSI design method has been proposed in order to reduce editing time and deposition resistivity of multilevel wires by FIB or laser CVD. In this method, modification elements, which consist of a pair of staked vias and a top-layer wire connecting the vias, are placed in unoccupied areas of LSI layout data. Placement positions of the elements and editing procedure corresponding to netlist revision specifications are automatically generated. It has been proved that this method can be used practically, because of demonstrating more than 90% placement ratio and at most 7.9% increase in capacitive load due to the placement.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Circuit editing / FIB / Laser CVD / planarization process / stacked via
Paper # CPM2000-143,ICD2000-176
Date of Issue

Conference Information
Committee CPM
Conference Date 2000/12/1(1days)
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Paper Information
Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Layout Design for LSI Circuit Modification
Sub Title (in English)
Keyword(1) Circuit editing
Keyword(2) FIB
Keyword(3) Laser CVD
Keyword(4) planarization process
Keyword(5) stacked via
1st Author's Name Norio KUJI
1st Author's Affiliation NTT Electronics Co.()
2nd Author's Name Tadao TAKEDA
2nd Author's Affiliation Nippon Telegraph & Telephone Co.
Date 2000/12/1
Paper # CPM2000-143,ICD2000-176
Volume (vol) vol.100
Number (no) 486
Page pp.pp.-
#Pages 7
Date of Issue