| Presentation | 2000/11/30 Evaluation of the DRAM manufacturing process with wafer-level-CSP technology through simulation analysis M. Tanabe, K. Nakamae, H. Fujioka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The wafer level chip size packaging process(WLCSP)is a new technology in which all of the IC packaging is performed at the wafer level. A WLCSP technology could maintain the cost of the IC packaging as a constant percentage of the total wafer cost since WLCSP reduces the cost of packaging the individual chips. In this paper, the effect of WLCSP on turnaround time (TAT)and cost is evaluated through an event-driven simulation analysis where the WLCSP for 64M DRAM is assumed. Results shows that the TAT and cost are reduced by about 20% and 15% respectively compared with those in the conventional wafer test, assembly and final test processes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Wafer-level-CSP / Packaging technology / simulation / TAT / cost |
| Paper # | CPM2000-140,ICD2000-173 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2000/11/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of the DRAM manufacturing process with wafer-level-CSP technology through simulation analysis |
| Sub Title (in English) | |
| Keyword(1) | Wafer-level-CSP |
| Keyword(2) | Packaging technology |
| Keyword(3) | simulation |
| Keyword(4) | TAT |
| Keyword(5) | cost |
| 1st Author's Name | M. Tanabe |
| 1st Author's Affiliation | Department of Information Systems Engineering, Faculty of Engineering, Osaka University() |
| 2nd Author's Name | K. Nakamae |
| 2nd Author's Affiliation | Department of Information Systems Engineering, Faculty of Engineering, Osaka University |
| 3rd Author's Name | H. Fujioka |
| 3rd Author's Affiliation | Department of Information Systems Engineering, Faculty of Engineering, Osaka University |
| Date | 2000/11/30 |
| Paper # | CPM2000-140,ICD2000-173 |
| Volume (vol) | vol.100 |
| Number (no) | 485 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |