| Presentation | 2000/11/30 Silicon Interposer Technology for High-density Package Mie Matsuo, Nobuo Hayasaka, Katsuya Okumura, Chiaki Takubo, Eiichi Hosomi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The achievement of rapid advances in integration density and performance of LSI devices is predicated on shrinking design rule of wiring and bump pitch on the organic substrate of a flip-chip package. However, decreasing the bump pitch and wiring rule raises the process cost of fabricating organic substrate. Moreover, it is difficult to obtain highly reliable connections between chip and organic substrate with smaller bumps due to the mismatching of the coefficient of the thermal expansion(CTE). To overcome these problems, a new interposer using silicon(Si)substrate with through plug is developed. The silicon interposer consists of a copper(Cu) / low relative dielectric constant(low-k)material interconnections and Cu through plugs in Si substrate. To fabricate interposer, high rate Si reactive ion etching(RIE)and Cu / low-k interconnections technologies are developed. In the demonstrated silicon interposer, the 10μm-pitch lines had 0.18dB/mm of attenuation and 8.5psec/mm of propagation delay at the frequency of 1GHz. The silicon interposer is a promising solution for future high-density flip-chip packaging. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Flip-chip-BGA / interposer / CTE / through plug / damascene / electrical character |
| Paper # | CPM2000-138,ICD2000-171 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2000/11/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Silicon Interposer Technology for High-density Package |
| Sub Title (in English) | |
| Keyword(1) | Flip-chip-BGA |
| Keyword(2) | interposer |
| Keyword(3) | CTE |
| Keyword(4) | through plug |
| Keyword(5) | damascene |
| Keyword(6) | electrical character |
| 1st Author's Name | Mie Matsuo |
| 1st Author's Affiliation | Process and Manufacturing Engineering Center Semiconductor Company, TOSHIBA Corp.() |
| 2nd Author's Name | Nobuo Hayasaka |
| 2nd Author's Affiliation | Process and Manufacturing Engineering Center Semiconductor Company, TOSHIBA Corp. |
| 3rd Author's Name | Katsuya Okumura |
| 3rd Author's Affiliation | Process and Manufacturing Engineering Center Semiconductor Company, TOSHIBA Corp. |
| 4th Author's Name | Chiaki Takubo |
| 4th Author's Affiliation | Process and Manufacturing Engineering Center Semiconductor Company, TOSHIBA Corp. |
| 5th Author's Name | Eiichi Hosomi |
| 5th Author's Affiliation | Process and Manufacturing Engineering Center Semiconductor Company, TOSHIBA Corp. |
| Date | 2000/11/30 |
| Paper # | CPM2000-138,ICD2000-171 |
| Volume (vol) | vol.100 |
| Number (no) | 485 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |