Presentation 2000/11/30
Sn-Ag Solder Bump Process
Hirokazu Ezawa, Masahiro Miyata,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have developed the eutectic Sn-Ag solder bump process for high pin count ULSIs which require Flip Chip interconnection. In the 2-step electroplating process using separate reactors for Ag and Sn each, the Sn-Ag alloy composition can be easily controlled by varying the thickness ratio of Ag and Sn in an Ag / Sn electroplated metal stack. The thick nega-resist plating mask with steep wall openings does not need complex plating current control. Thus, better within-uniformity of bump height and solder alloy composition can be easily obtained, which leads to a robust mass-producing.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Sn-Ag eutectic alloy / Solder Bump / Flip Chip / Electroplating / Thick nega-resist mask
Paper # CPM2000-136,ICD2000-169
Date of Issue

Conference Information
Committee CPM
Conference Date 2000/11/30(1days)
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Paper Information
Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Sn-Ag Solder Bump Process
Sub Title (in English)
Keyword(1) Sn-Ag eutectic alloy
Keyword(2) Solder Bump
Keyword(3) Flip Chip
Keyword(4) Electroplating
Keyword(5) Thick nega-resist mask
1st Author's Name Hirokazu Ezawa
1st Author's Affiliation Toshiba Corporation Semiconductor Company Advanced ULSI Process Engineering Dept.()
2nd Author's Name Masahiro Miyata
2nd Author's Affiliation Toshiba Corporation Semiconductor Company Advanced ULSI Process Engineering Dept.
Date 2000/11/30
Paper # CPM2000-136,ICD2000-169
Volume (vol) vol.100
Number (no) 485
Page pp.pp.-
#Pages 8
Date of Issue