| Presentation | 1998/12/10 Advanced ATM Switching System Hardware Technologies based on MCM-D and stacked RAMs Naoaki Yamanaka, Tomoaki Kawamura, Akio Harada, Katsumi Kaizu, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes newly developed advanced ATM switching system hardware structures based on MCM-D micro-processor modules. The Si-Substrate MCM-D technology which integrates micro-processor, interface control and peripheral control custom VLSIs, high-speed S-RAMs, and FPGAs(Field Programmable Gate Arrays)is employed. An MCM-D micro-processor module is realized by combining a Motorola 68030, high-performance ASICs, and high-speed S-RAM caches. This is made possible by high density packaging and high-speed 4M-byte with parity cache using 25 ns access to 4-Mbit of S-RAM memory. The MCM employs 12 S-RAMs, possible with the stacked RAM technique, to reduce the module size by 7/8 compared to conventional surface mounting modules. This micro-processor module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MCM / ATM / Packaging / Stacked RAM / Microprocessor |
| Paper # | CPM98-156,ICD98-235 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 1998/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Advanced ATM Switching System Hardware Technologies based on MCM-D and stacked RAMs |
| Sub Title (in English) | |
| Keyword(1) | MCM |
| Keyword(2) | ATM |
| Keyword(3) | Packaging |
| Keyword(4) | Stacked RAM |
| Keyword(5) | Microprocessor |
| 1st Author's Name | Naoaki Yamanaka |
| 1st Author's Affiliation | NTT Network Service systems Laboratories() |
| 2nd Author's Name | Tomoaki Kawamura |
| 2nd Author's Affiliation | NTT Network Service systems Laboratories |
| 3rd Author's Name | Akio Harada |
| 3rd Author's Affiliation | NTT Network Service systems Laboratories |
| 4th Author's Name | Katsumi Kaizu |
| 4th Author's Affiliation | NTT Network Service systems Laboratories |
| Date | 1998/12/10 |
| Paper # | CPM98-156,ICD98-235 |
| Volume (vol) | vol.98 |
| Number (no) | 456 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |