| Presentation | 2001/6/22 A Pipelined Scheduling Method Considering Conditional Branches Makoto IKENAGA, Katsumi HARASHIMA, Toshirou KUTSUWA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For data flow graphs with conditional branches most of conventional pipelined scheduling mothods have not been able to obtain optimal schedules in regard to hardware area, because they have assigned operations in each conditional branch to individual hardware units. This paper proposes a pipelined scheduling for signal-processing circuits with conditional branches. In order to minimize hardware area under the constraint corresponding to processing speed of the slowest part in a chip, our approach schedules the whole a signal processing system including the conditions and branches. First, our approach assigns operations to each control step so as to close to the same number of operations in conditional branches. Next, it closes the same number of operations in each control step to maximal number of operations. The experimental results show that our proposed approach is effective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-level Synthesis / signal processing / conditional branches / pipelined scheduling |
| Paper # | CAS2001-39,VLD2001-56,DSP2001-58 |
| Date of Issue |
| Conference Information | |
| Committee | CAS |
|---|---|
| Conference Date | 2001/6/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Pipelined Scheduling Method Considering Conditional Branches |
| Sub Title (in English) | |
| Keyword(1) | High-level Synthesis |
| Keyword(2) | signal processing |
| Keyword(3) | conditional branches |
| Keyword(4) | pipelined scheduling |
| 1st Author's Name | Makoto IKENAGA |
| 1st Author's Affiliation | Dept. of Electronics, Osaka Institute of Technology() |
| 2nd Author's Name | Katsumi HARASHIMA |
| 2nd Author's Affiliation | Dept. of Electronics, Osaka Institute of Technology |
| 3rd Author's Name | Toshirou KUTSUWA |
| 3rd Author's Affiliation | Dept. of Electronics, Osaka Institute of Technology |
| Date | 2001/6/22 |
| Paper # | CAS2001-39,VLD2001-56,DSP2001-58 |
| Volume (vol) | vol.101 |
| Number (no) | 142 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |