| Presentation | 2000/6/16 FPGA Implementation of FIR Digital Filters with CSD Coefficients and Minimum Critical Path Mitsuru YAMADA, Akinori NISHIHARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A method to implement very fast and low-complexity FIR digital filters on field programmable gate arrays (FPGAs) is proposed. Filters can operate fast with less complexity when multipliers with coefficients expressed as canonic signed digit (CSD) code are realized with wired-shifters, adders and subtracters. Since FPGAs have special internal structures, insertion of pipeline registers reduces the critical path length with only a little increase in their die area. The number of pipeline registers is limited by using an equivalent transformation on signal flow graphs. Resultant filters can operate with the minimum critical path length of a single adder. In an actual implementation on XC4028XL-1, the proposed technique made the sampling frequency double with 5% and 29% increases in die area and latency, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FIR digital filter / CSD / FPGA / pipelining / critical path |
| Paper # | CAS2000-34,VLD2000-43,DSP2000-55 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2000/6/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of FIR Digital Filters with CSD Coefficients and Minimum Critical Path |
| Sub Title (in English) | |
| Keyword(1) | FIR digital filter |
| Keyword(2) | CSD |
| Keyword(3) | FPGA |
| Keyword(4) | pipelining |
| Keyword(5) | critical path |
| 1st Author's Name | Mitsuru YAMADA |
| 1st Author's Affiliation | Graduate School of Science and Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Akinori NISHIHARA |
| 2nd Author's Affiliation | Graduate School of Science and Engineering, Tokyo Institute of Technology |
| Date | 2000/6/16 |
| Paper # | CAS2000-34,VLD2000-43,DSP2000-55 |
| Volume (vol) | vol.100 |
| Number (no) | 119 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |