Presentation 2000/6/16
Design of Signal Word Decomposed Filters with Reduced VLSI Gate Count
Kouhei HOSOKAWA, Mitsuhiko YAGYU, Akinori NISHIHARA,
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Abstract(in English) A new design of signal word decomposed filters(SWDFs) is proposed. Unlike the conventional method which only considers the number of full adders included in multipliers, all components implemented on VLSI are taken into account for the evaluation of filter complexity. Then the constraint that non-zero coefficients of less significant subfilter be equal to those of more significant subfilter is found to be quite effective in simplifying the structure and yet keeping the filter performance. The design is formulated as a linea programming. As a result, SWDFs with reduced gate count are designed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Signal Word Decomposed Filters / Circuit Complexity
Paper # CAS2000-33,VLD2000-42,DSP2000-54
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Committee CAS
Conference Date 2000/6/16(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Signal Word Decomposed Filters with Reduced VLSI Gate Count
Sub Title (in English)
Keyword(1) Signal Word Decomposed Filters
Keyword(2) Circuit Complexity
1st Author's Name Kouhei HOSOKAWA
1st Author's Affiliation Graduate School of Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Mitsuhiko YAGYU
2nd Author's Affiliation Texas Instruments CORPORATION. Tsukuba Research & Development Center Ltd.
3rd Author's Name Akinori NISHIHARA
3rd Author's Affiliation The Center for Research and Development of Educational Technology, Tokyo Institute of Technology
Date 2000/6/16
Paper # CAS2000-33,VLD2000-42,DSP2000-54
Volume (vol) vol.100
Number (no) 119
Page pp.pp.-
#Pages 6
Date of Issue