| Presentation | 1999/1/21 Mixed Analog and Digital 240Mbps CMOS-EPRML Read Channel Chip for Hard Disk Drives Tatsuji Matsuura, Eiki Imaizumi, Kenji Toyota, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A mixed analog and digital 240-Mbps CMOS extended-partial-response maximum-likelihood(EPRML)read/write channel LSI chip for hard disk drives has been developed. A 240Mbps transfer rate was achieved by using fine 0.35um-CMOS precess. Power consumption of 1W was achieved by using a 3.3-V power supply and a 3.3-V CMOS analog circuit design. A filter circuit architecture suitable for fine CMOS device has been developped using proposed gain tuning circuit. An interleaved sub-ranging pipeline look-ahead A/D converter architecture has been developped to reduce power consumption. The read-mode channel path combines an acquisition-mode analog phase-locked loop(PLL)and a tracking-mode precision digital PLL, enabling the use of a long-latency pipeline A/D converter in the digital PLL. Consequently, a bit error rate of 10^<**>(-9)at a signal-to-noise ratio of 24.5 dB has been achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / PRML / filter / A/D converter / analog and mixed-signal IC |
| Paper # | CAS98-71 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 1999/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mixed Analog and Digital 240Mbps CMOS-EPRML Read Channel Chip for Hard Disk Drives |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | PRML |
| Keyword(3) | filter |
| Keyword(4) | A/D converter |
| Keyword(5) | analog and mixed-signal IC |
| 1st Author's Name | Tatsuji Matsuura |
| 1st Author's Affiliation | Second System LSI Engineering Dept., System LSI Business Operation, System LSI Business Div. Semiconductor & Integrated Circuits Group, Hitachi, Ltd.() |
| 2nd Author's Name | Eiki Imaizumi |
| 2nd Author's Affiliation | Hitachi ULSI Systems, Ltd. |
| 3rd Author's Name | Kenji Toyota |
| 3rd Author's Affiliation | Second System LSI Engineering Dept., System LSI Business Operation, System LSI Business Div. Semiconductor & Integrated Circuits Group, Hitachi, Ltd. |
| Date | 1999/1/21 |
| Paper # | CAS98-71 |
| Volume (vol) | vol.98 |
| Number (no) | 515 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |