Presentation 1998/6/26
System-Level Energy Optimization for Embedded Systems with a Variable Datapath Width Processor
Akihiko INOUE, Hiroyuki TOMIYAMA, Tohru ISHIHARA, Hiroto YASUURA,
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Abstract(in English) In this paper, a system-level low power design methodology for processor based embedded systems is proposed. Our objective is to minimize energy consumed by redundant bits, which are unused during execution of programs, by means of reducing the datapath whdth of processors. In our design environment, system designers can determine the optimal datapath width for each application with trading cost, performance and power consumption of systems. Experimental results show the effectiveness of our approach.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low Power Design / Hardware/Software Codesign / System LSI
Paper # CAS98-29,VLD98-29,DSP98-58
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Committee CAS
Conference Date 1998/6/26(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) System-Level Energy Optimization for Embedded Systems with a Variable Datapath Width Processor
Sub Title (in English)
Keyword(1) Low Power Design
Keyword(2) Hardware/Software Codesign
Keyword(3) System LSI
1st Author's Name Akihiko INOUE
1st Author's Affiliation Department of Computer Science and Communication Engineering, Kyusyu University()
2nd Author's Name Hiroyuki TOMIYAMA
2nd Author's Affiliation Department of Computer Science and Communication Engineering, Kyusyu University
3rd Author's Name Tohru ISHIHARA
3rd Author's Affiliation Department of Computer Science and Communication Engineering, Kyusyu University
4th Author's Name Hiroto YASUURA
4th Author's Affiliation Department of Computer Science and Communication Engineering, Kyusyu University
Date 1998/6/26
Paper # CAS98-29,VLD98-29,DSP98-58
Volume (vol) vol.98
Number (no) 140
Page pp.pp.-
#Pages 8
Date of Issue