Presentation 1998/6/26
Barrier Synchronizer LSI which can Resolve Pseudo Dependency caused by Partial Order Barrier Groups
Tatsuo TSUCHIE, Tetsuo HIRONAKA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In multiprocessor system, overhead seen in synchronizing processors gives a great impact in performance. To make this overhead small many synchronizing architecture was proposed in the past. But there are not so many synchronizing architecture, which can resolve pseudo dependency caused by partial order barrier groups. This paper proposes barrier synchronization architecture called GMB (Group Manageable Barrier), with the ability to resolve such dependency. This paper also presents the implementation of the synchronizer on 9.0mm square LSI manufactured by ROHM.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) synchronization architecture / synchronization group / barrier synchronizatiohn / Partial Order / Multiprocessor / VLSI
Paper # CAS98-26,VLD98-26,DSP98-55
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Conference Information
Committee CAS
Conference Date 1998/6/26(1days)
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Paper Information
Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Barrier Synchronizer LSI which can Resolve Pseudo Dependency caused by Partial Order Barrier Groups
Sub Title (in English)
Keyword(1) synchronization architecture
Keyword(2) synchronization group
Keyword(3) barrier synchronizatiohn
Keyword(4) Partial Order
Keyword(5) Multiprocessor
Keyword(6) VLSI
1st Author's Name Tatsuo TSUCHIE
1st Author's Affiliation Graduate School of Information Sciences, Hiroshima City University()
2nd Author's Name Tetsuo HIRONAKA
2nd Author's Affiliation Graduate School of Information Sciences, Hiroshima City University
Date 1998/6/26
Paper # CAS98-26,VLD98-26,DSP98-55
Volume (vol) vol.98
Number (no) 140
Page pp.pp.-
#Pages 8
Date of Issue