Presentation 1998/6/26
Radix-4 Dividers without Using Quotient Digit Selection Tables
Osamu MIURA, Takafumi AOKI, Tatsuo HIGUCHI,
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Abstract(in English) This paper presents the design and evaluation of radix-4 parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By per-scaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed redix-4 divider architecture achieves faster computation with less hardware complexity, in comparison with the binary counterparts.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Computer arithmetic / SRT division / Quotient digit selection tables / High-radix division / Signed-digit number systems VLSI
Paper # CAS98-24,VLD98-24,DSP98-53
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Committee CAS
Conference Date 1998/6/26(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Radix-4 Dividers without Using Quotient Digit Selection Tables
Sub Title (in English)
Keyword(1) Computer arithmetic
Keyword(2) SRT division
Keyword(3) Quotient digit selection tables
Keyword(4) High-radix division
Keyword(5) Signed-digit number systems VLSI
1st Author's Name Osamu MIURA
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Takafumi AOKI
2nd Author's Affiliation PRESTO, Japan Science and Technology Corporation
3rd Author's Name Tatsuo HIGUCHI
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 1998/6/26
Paper # CAS98-24,VLD98-24,DSP98-53
Volume (vol) vol.98
Number (no) 140
Page pp.pp.-
#Pages 8
Date of Issue