| Presentation | 1998/6/26 Iterative Generation of Steiner Trees by Flip for Optimum Interconnection Layout Yasuhiro Takashima, Tsuyoshi Kurasawa, Shigetoshi Nakatake, Yoji Kajitani, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The technology of semi-conductor is going into a deep submicron level. The interconnection is becoming critical to the performance. For a net, there exist some construction methods of interconnection. But, under the constraints of delay or shape of routing region, it is not true that the partial optimal solution leads the whole optimal solution. It is said that a searching algorithm is the best choice. We propose a searching algorithm, called flip, for optimizing multiple objectives, implement our algorithm based on the flip, and experiment to show the basic performance of flip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | routing / plane graph / Steiner tree / flip / multiple objectives / complicated routing regions |
| Paper # | CAS98-21,VLD98-21,DSP98-50 |
| Date of Issue |
| Conference Information | |
| Committee | CAS |
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| Conference Date | 1998/6/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Iterative Generation of Steiner Trees by Flip for Optimum Interconnection Layout |
| Sub Title (in English) | |
| Keyword(1) | routing |
| Keyword(2) | plane graph |
| Keyword(3) | Steiner tree |
| Keyword(4) | flip |
| Keyword(5) | multiple objectives |
| Keyword(6) | complicated routing regions |
| 1st Author's Name | Yasuhiro Takashima |
| 1st Author's Affiliation | Inforemation Science, Japan Advanced Inst. of Science and Tech.() |
| 2nd Author's Name | Tsuyoshi Kurasawa |
| 2nd Author's Affiliation | Dept. of Elcetrical and Electronic Engrg., Tokyo Inst. of Tech. |
| 3rd Author's Name | Shigetoshi Nakatake |
| 3rd Author's Affiliation | Dept. of Elcetrical and Electronic Engrg., Tokyo Inst. of Tech. |
| 4th Author's Name | Yoji Kajitani |
| 4th Author's Affiliation | Dept. of Elcetrical and Electronic Engrg., Tokyo Inst. of Tech. |
| Date | 1998/6/26 |
| Paper # | CAS98-21,VLD98-21,DSP98-50 |
| Volume (vol) | vol.98 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |