| Presentation | 1998/6/26 Redundant Binary Adder Representing 1 Digit by 3 Bits and Its Application to Multiplier Mitsuki Hinosugi, Masato Saito, Katsumi Abukawa, Yoshitaka Tsunekawa, Mamoru Miura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, a new redundant binary adder, which is combined representations of 1 digit by 2 bits and 3 bits, is proposed. This uses 3 bits representation to input and output signals, in order to detect speedily which adding result is 1 or -1. To control the increase in the amount of hardware by using 3 bits representation, 2 bits representation is used to the intermediate sum and intermediate carry. And, the gate numbers and delay time are calculated from the logical expression. Furthermore, by using PARTHENON, this adder is evaluated. As a result, it is clear that this adder which is hardware-efficient as well as high-speed is realizable. Finally, as application of this adder, it applies to the multiplier and is evaluated. Consequently, the availability of the proposed adder is shown. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | redundant binary adder / high-speed / multiplier / VLSI evaluation |
| Paper # | CAS98-19,VLD98-19,DSP98-48 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 1998/6/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Redundant Binary Adder Representing 1 Digit by 3 Bits and Its Application to Multiplier |
| Sub Title (in English) | |
| Keyword(1) | redundant binary adder |
| Keyword(2) | high-speed |
| Keyword(3) | multiplier |
| Keyword(4) | VLSI evaluation |
| 1st Author's Name | Mitsuki Hinosugi |
| 1st Author's Affiliation | Faculty of Engineering, Iwate University() |
| 2nd Author's Name | Masato Saito |
| 2nd Author's Affiliation | Faculty of Engineering, Iwate University |
| 3rd Author's Name | Katsumi Abukawa |
| 3rd Author's Affiliation | Faculty of Engineering, Iwate University |
| 4th Author's Name | Yoshitaka Tsunekawa |
| 4th Author's Affiliation | Faculty of Engineering, Iwate University |
| 5th Author's Name | Mamoru Miura |
| 5th Author's Affiliation | Faculty of Engineering, Iwate University |
| Date | 1998/6/26 |
| Paper # | CAS98-19,VLD98-19,DSP98-48 |
| Volume (vol) | vol.98 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |