Presentation 1995/6/23
A VLSI Architecture Oriented for Hyper Parallel Arrangement on Non-Linear Signal Processing
Toshihiro Kobayashi, Yoshikazu Miyanaga, Koji Tochinai,
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Abstract(in English) An adaptive and nonlinear digital signal processing is developed in parallel / pipelined VLSI system by using a self-organized clustering network in this report. This system has an actual purpose applying to the field of speech information processing. The above VLSI system is designed for a real time processing on which every required calculation should be executed in a given certain time. If the total number of clusters which corresponds to the size of network has no restriction, the total processing time should not depend on its number. Accordingly a novel parallel processing for such clustering is required. In this report, although only logic designing has been accomplished, some difficulties and important consideration are presented.
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Keyword(in English) Self-Organized Clustering / Hyper Parallel Arrangement / Real Time Signal Processing
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Committee CAS
Conference Date 1995/6/23(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A VLSI Architecture Oriented for Hyper Parallel Arrangement on Non-Linear Signal Processing
Sub Title (in English)
Keyword(1) Self-Organized Clustering
Keyword(2) Hyper Parallel Arrangement
Keyword(3) Real Time Signal Processing
1st Author's Name Toshihiro Kobayashi
1st Author's Affiliation Faculty of Engineering, Hokkaido University()
2nd Author's Name Yoshikazu Miyanaga
2nd Author's Affiliation Faculty of Engineering, Hokkaido University
3rd Author's Name Koji Tochinai
3rd Author's Affiliation Faculty of Engineering, Hokkaido University
Date 1995/6/23
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Volume (vol) vol.95
Number (no) 106
Page pp.pp.-
#Pages 8
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