Presentation 1995/6/23
A performance-oriented macrocell design methodology for image processing LSIs
R. Kusaba, T. Watanabe, T. Minami, T. Kondo, H. Matsuda,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Image processing LSIs require high performance, high packing densities and short TATs. This paper proposes a performance-oriented macrocell design methodology that satisfies these requirements. The method (1)evaluates delay, (2)shortens TAT by leafcell generation, (3)takes redesign and hierarchical design into consideration, (4)and can be applied to non-repeated layout structures. Several image processing LSIs have been designed with an average of 5.7KTr/mm^2 in 15-63K transistors and with a macrocell in the processing speed of 7.5nsec.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) datapath / macrocell / leafcell / LSI CAD / LSI design
Paper #
Date of Issue

Conference Information
Committee CAS
Conference Date 1995/6/23(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A performance-oriented macrocell design methodology for image processing LSIs
Sub Title (in English)
Keyword(1) datapath
Keyword(2) macrocell
Keyword(3) leafcell
Keyword(4) LSI CAD
Keyword(5) LSI design
1st Author's Name R. Kusaba
1st Author's Affiliation NTT LSI Laboratories()
2nd Author's Name T. Watanabe
2nd Author's Affiliation NTT LSI Laboratories
3rd Author's Name T. Minami
3rd Author's Affiliation NTT LSI Laboratories
4th Author's Name T. Kondo
4th Author's Affiliation NTT LSI Laboratories
5th Author's Name H. Matsuda
5th Author's Affiliation NTT LSI Laboratories
Date 1995/6/23
Paper #
Volume (vol) vol.95
Number (no) 106
Page pp.pp.-
#Pages 6
Date of Issue