| Presentation | 1996/6/24 Fault-Tolerant Meshes with Efficient Layouts Toshinori Yamada, Shuichi Ueno, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a practical fault tolerant architecture for mesh parallel machines that has only one spare processor and has only six communication links per processor while tolerating one processor fault and one communication link fault, or two communication link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most six. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Mesh / Fault-Tolerant Graph / Embedding / Layout / Wire Length |
| Paper # | CAS96-5,VLD96-5,DSP96-25 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 1996/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fault-Tolerant Meshes with Efficient Layouts |
| Sub Title (in English) | |
| Keyword(1) | Mesh |
| Keyword(2) | Fault-Tolerant Graph |
| Keyword(3) | Embedding |
| Keyword(4) | Layout |
| Keyword(5) | Wire Length |
| 1st Author's Name | Toshinori Yamada |
| 1st Author's Affiliation | Department of Electrical and Electronic Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Shuichi Ueno |
| 2nd Author's Affiliation | Department of Electrical and Electronic Engineering, Tokyo Institute of Technology |
| Date | 1996/6/24 |
| Paper # | CAS96-5,VLD96-5,DSP96-25 |
| Volume (vol) | vol.96 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |