Presentation 1996/3/18
A study of digital correlator for high speed DS-CDMA transmission
Hiroyuki Nakase, Eisuke Kudoh, Shigeaki Ogose,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) For the purpose of multi-media signal transmission with a bit-rate of more than 64 kbit/s through DS-CDMA system, a digital correlator has been implemented and evaluated in laboratory test measurement on 2 GHz band. The correlator is based on digital delay-locked loop (DLL). Measurement was conducted when chip rate is 2.048Mchip/s and spreading-code length is 15 chip under the perfect transmitter power control (TPC). The result shows that the bit-error-rate (BER) performance is agree well with the theoretical values and the degradation of Eb/No for 10-5 BER is 2 dB. This correlator can operate at a bit-rate over 384 kbit/s if we change some circuit parameters.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) DS-CDMA / Digital DLL
Paper # IT95-63,ISEC95-58,SST95-124
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Committee IT
Conference Date 1996/3/18(1days)
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Paper Information
Registration To Information Theory (IT)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study of digital correlator for high speed DS-CDMA transmission
Sub Title (in English)
Keyword(1) DS-CDMA
Keyword(2) Digital DLL
1st Author's Name Hiroyuki Nakase
1st Author's Affiliation NTT Wireless Systems Laboratories()
2nd Author's Name Eisuke Kudoh
2nd Author's Affiliation NTT Wireless Systems Laboratories
3rd Author's Name Shigeaki Ogose
3rd Author's Affiliation NTT Wireless Systems Laboratories
Date 1996/3/18
Paper # IT95-63,ISEC95-58,SST95-124
Volume (vol) vol.95
Number (no) 590
Page pp.pp.-
#Pages 6
Date of Issue