| Presentation | 2002/1/10 Multicast ATM Switch and Scheduling Algorithm in Asymmetric Traffic Takahiro NISHIMURA, Katsutoshi OHMAE, Hiroaki KITA, Hiroki TANIDA, Hiromi OKADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | ATM switching systems are expected to support a great deal of multicast connections in addition to the conventional point-to-point connections. Multicasting or the ability to provide point-to-multipoint connections is an important feature for switching networks intended to support B-ISDN. We have already proposed a design to support multicasting in ATM switch, called SSMAP (Singlecast Stuffed Multicast Advanced Processing) ATM switch, which can transmit multicast traffic effectively. In this paper, we propose new switch architecture using SSMAP ATM switch, called Buffer-counter SSMAP ATM switch. We evaluate the characteristics of Buffer-counter SSMAP ATM switch in asymmetric traffic, and multicast scheduling methods by computer simulations, and show their validity. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multicast / Asymmetric Traffic / SSMAP ATM Switch / Scheduling / MMBP/MS Model |
| Paper # | 2001-IN-148,2001-TM-73,2001-OFS-64 |
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| Conference Information | |
| Committee | IN |
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| Conference Date | 2002/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Networks (IN) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multicast ATM Switch and Scheduling Algorithm in Asymmetric Traffic |
| Sub Title (in English) | |
| Keyword(1) | Multicast |
| Keyword(2) | Asymmetric Traffic |
| Keyword(3) | SSMAP ATM Switch |
| Keyword(4) | Scheduling |
| Keyword(5) | MMBP/MS Model |
| 1st Author's Name | Takahiro NISHIMURA |
| 1st Author's Affiliation | Information Network Laboratory, Department of Electronics Engineering, Faculty of Engineering, Kansai University() |
| 2nd Author's Name | Katsutoshi OHMAE |
| 2nd Author's Affiliation | Information Network Laboratory, Department of Electronics Engineering, Faculty of Engineering, Kansai University |
| 3rd Author's Name | Hiroaki KITA |
| 3rd Author's Affiliation | Information Network Laboratory, Department of Electronics Engineering, Faculty of Engineering, Kansai University |
| 4th Author's Name | Hiroki TANIDA |
| 4th Author's Affiliation | Information Network Laboratory, Department of Electronics Engineering, Faculty of Engineering, Kansai University |
| 5th Author's Name | Hiromi OKADA |
| 5th Author's Affiliation | Information Network Laboratory, Department of Electronics Engineering, Faculty of Engineering, Kansai University |
| Date | 2002/1/10 |
| Paper # | 2001-IN-148,2001-TM-73,2001-OFS-64 |
| Volume (vol) | vol.101 |
| Number (no) | 558 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |