| Presentation | 2001/9/7 A study on a configuration of high capacity packet switch based on deflection routing multistage network appropriate for implementation on LSI chip Hiroaki Morino, Nguyen Hoaison, Hitoshi Aida, Tadao Saito, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed a switch of deflection routing and shortest path routing multistage network for high capacity switch fabric handling thousands of input ports and output ports for terabit IP router. It is called ring shuffle pattern switch. In this paper, a configuration of circuits of ring shuffle pattern switch is examined, and two proposals are described. The first proposal is a new packet scheduling method of a switch element working efficiently for variable length packet switching. The second proposal is a new input port connection pattern in multistage network to improve switch element utilization compared with conventional methods. Simulation and circuit design of 8×8 switch element for FPGA is performed, and a perspective that implementation of 64×64 switch by the proposed method is shown. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IP router / switch fabric / multistage network / deflection routing / shortest path routing |
| Paper # | NS2001-117,IN2001-81,CS2001-78 |
| Date of Issue |
| Conference Information | |
| Committee | IN |
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| Conference Date | 2001/9/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
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| Paper Information | |
| Registration To | Information Networks (IN) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on a configuration of high capacity packet switch based on deflection routing multistage network appropriate for implementation on LSI chip |
| Sub Title (in English) | |
| Keyword(1) | IP router |
| Keyword(2) | switch fabric |
| Keyword(3) | multistage network |
| Keyword(4) | deflection routing |
| Keyword(5) | shortest path routing |
| 1st Author's Name | Hiroaki Morino |
| 1st Author's Affiliation | Research and Development Initiative Chuo University() |
| 2nd Author's Name | Nguyen Hoaison |
| 2nd Author's Affiliation | School of Engineering, The University of Tokyo |
| 3rd Author's Name | Hitoshi Aida |
| 3rd Author's Affiliation | Graduate School of Frontier Sciences University of Tokyo |
| 4th Author's Name | Tadao Saito |
| 4th Author's Affiliation | Faculty of Science and Engineering Chuo University |
| Date | 2001/9/7 |
| Paper # | NS2001-117,IN2001-81,CS2001-78 |
| Volume (vol) | vol.101 |
| Number (no) | 289 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |