Presentation | 2000/9/14 A throughput improvement on Routers by the control of packet size Toshikatsu Kanda, Kazunori Shimamura, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The networks are facilitating higher throughput and more heterogeneity, especially on the threshold of backbone and access networks. The Internet is composed of these networks. The number of the connection is increasing at this moment. On the other hand, node processor would be a bottleneck in respect to the high throughput. Then, authors propose Packet Assembly. This aims to abridge the headers of packets for the utilization of bandwidth and the decrease of the number of packets for the reduction of processor load, based on the fact that there are many packets much smaller than Maximum Transferable Unit(MTU). |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | IP / packet assembly / processor load / packet size / traffic / throughput |
Paper # | SSE2000-114,IN2000-65,CS2000-45 |
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Conference Information | |
Committee | IN |
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Conference Date | 2000/9/14(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Information Networks (IN) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A throughput improvement on Routers by the control of packet size |
Sub Title (in English) | |
Keyword(1) | IP |
Keyword(2) | packet assembly |
Keyword(3) | processor load |
Keyword(4) | packet size |
Keyword(5) | traffic |
Keyword(6) | throughput |
1st Author's Name | Toshikatsu Kanda |
1st Author's Affiliation | Kochi Research Center, Telecommunications Advancement Organization of Japan() |
2nd Author's Name | Kazunori Shimamura |
2nd Author's Affiliation | Kochi University of Technology |
Date | 2000/9/14 |
Paper # | SSE2000-114,IN2000-65,CS2000-45 |
Volume (vol) | vol.100 |
Number (no) | 299 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |