| Presentation | 1995/9/29 Design of the Shared-Buffering ATM Switch LSI chipset using 0.5-μmCMOS technology Yasuhito SASAKI, Hideaki YAMANAKA, Harufusa KONDOH, Hirotaka SAITO, Munenori TSUZUKI, Shigeki KOHAMA, Hirotoshi YAMADA, Yoshio MATSUDA, Kazuyoshi OSHIMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A newly proposed funnel-structured expandable architecture in the shared buffer type ATM switch and a searchable address queueing scheme are presented. The funnel structure gives flexible capability to build up various sizes of ATM switches. The searchable address queue, in which all the addresses of the stored cells for different output ports are queued in single-FIFO hardware, can reduce the total memory capacity drastically and enables the address queue to be contained inside the LSI chip. This technique has also great advantage for implementing the mulicast and multilevel priority-control functions. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 0.5μm CMOS techno1ogy / shared buffering / ATM switch / LSI / multicast / priority control |
| Paper # | SSE95-76,IN95-47,CS95-96 |
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| Conference Information | |
| Committee | IN |
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| Conference Date | 1995/9/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Information Networks (IN) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of the Shared-Buffering ATM Switch LSI chipset using 0.5-μmCMOS technology |
| Sub Title (in English) | |
| Keyword(1) | 0.5μm CMOS techno1ogy |
| Keyword(2) | shared buffering |
| Keyword(3) | ATM switch |
| Keyword(4) | LSI |
| Keyword(5) | multicast |
| Keyword(6) | priority control |
| 1st Author's Name | Yasuhito SASAKI |
| 1st Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hideaki YAMANAKA |
| 2nd Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 3rd Author's Name | Harufusa KONDOH |
| 3rd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 4th Author's Name | Hirotaka SAITO |
| 4th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 5th Author's Name | Munenori TSUZUKI |
| 5th Author's Affiliation | Information &Communication Systems Development Center, Mitsubishi Electric Corporation |
| 6th Author's Name | Shigeki KOHAMA |
| 6th Author's Affiliation | Communication Equipment Works, Mitsubishi Electric Corporation |
| 7th Author's Name | Hirotoshi YAMADA |
| 7th Author's Affiliation | Information Technology R&D Center, Mitsubishi Electric Corporation |
| 8th Author's Name | Yoshio MATSUDA |
| 8th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 9th Author's Name | Kazuyoshi OSHIMA |
| 9th Author's Affiliation | Information &Communication Systems Development Center, Mitsubishi Electric Corporation |
| Date | 1995/9/29 |
| Paper # | SSE95-76,IN95-47,CS95-96 |
| Volume (vol) | vol.95 |
| Number (no) | 267 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |