Presentation 2001/11/15
MPEG-4 Video Decoder Using VLIW Based Media Processor
Masao ISHIGURO, Yoshifumi FUJIKAWA, Muneaki TAMAGUCHI, Kazushige HIROI, Atsuo KAWAGUCHI, Norihiro SUZUKI,
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Abstract(in English) We have developed the MPEWG-4 Simple Profile Video decoder using the MAPCA media processor based on the VLIW architecture. The MAPCA supports programmable video, image, and signal processing software implementation of compression and decompression algorithms, so the MAPCA matches the cost and performance features of dedicated fixed function chips, with the added flexibility to rapidly respond to evolving standards. By efficient use of SIMD instructions, the DMA engine "Data Streamer", and the VLx co-processor, the decoder can decode a video stream of CIF (352×288 pixel), 30fps and 38kbps at 50MHz of the CPU clock.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Media Processor / MPEG-4 / Video / Decoder / VLIW
Paper # IE2001-120
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Committee IE
Conference Date 2001/11/15(1days)
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Registration To Image Engineering (IE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) MPEG-4 Video Decoder Using VLIW Based Media Processor
Sub Title (in English)
Keyword(1) Media Processor
Keyword(2) MPEG-4
Keyword(3) Video
Keyword(4) Decoder
Keyword(5) VLIW
1st Author's Name Masao ISHIGURO
1st Author's Affiliation Hitachi, Ltd. Systems Development Laboratory()
2nd Author's Name Yoshifumi FUJIKAWA
2nd Author's Affiliation Hitachi, Ltd. Systems Development Laboratory
3rd Author's Name Muneaki TAMAGUCHI
3rd Author's Affiliation Central Research Laboratory
4th Author's Name Kazushige HIROI
4th Author's Affiliation Hitachi, Ltd. Systems Development Laboratory
5th Author's Name Atsuo KAWAGUCHI
5th Author's Affiliation Hitachi, Ltd. Systems Development Laboratory
6th Author's Name Norihiro SUZUKI
6th Author's Affiliation Central Research Laboratory
Date 2001/11/15
Paper # IE2001-120
Volume (vol) vol.101
Number (no) 456
Page pp.pp.-
#Pages 6
Date of Issue