Presentation 1993/11/19
45Mb/s CLAD implementation and experimental results in ATM networks
Hitoshi Uematsu, Hiromi Ueda, Kazumitsu Maki, Hiroyuki Kasai,
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Abstract(in English) Cell assembly and disassembly function is indispensable for an ATM network.We implemented a 45Mb, s CLAD which has the CBR signal timing recovery mechanism using SRTS(Synchronous Residual Time Stamp)method defined by ITUT Recommendation I.363.SRTS method generates low frequency jitter in the CBR signal like a frequency justification with pulse stuffing.We evaluate the jitter using the implemented CLAD.When cell loss or cell misdelivery occurs,the CLAD maintains the bit count integrity of CBR signal using SN and SNP of AAL type 1.45Mb/s digital video transmission and computer communications between FDDI-LANs are verified by using the CLAD in the VI&P trial.
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Keyword(in English) ATM / CBR / adaptation layer / SRTS / jitter / timing
Paper # SAT93-64,CS93-133
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Committee SAT
Conference Date 1993/11/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 45Mb/s CLAD implementation and experimental results in ATM networks
Sub Title (in English)
Keyword(1) ATM
Keyword(2) CBR
Keyword(3) adaptation layer
Keyword(4) SRTS
Keyword(5) jitter
Keyword(6) timing
1st Author's Name Hitoshi Uematsu
1st Author's Affiliation Nippon Telegraph and Telephone Corp.()
2nd Author's Name Hiromi Ueda
2nd Author's Affiliation Nippon Telegraph and Telephone Corp.
3rd Author's Name Kazumitsu Maki
3rd Author's Affiliation Nippon Telegraph and Telephone Corp.
4th Author's Name Hiroyuki Kasai
4th Author's Affiliation Nippon Telegraph and Telephone Corp.
Date 1993/11/19
Paper # SAT93-64,CS93-133
Volume (vol) vol.93
Number (no) 336
Page pp.pp.-
#Pages 8
Date of Issue