Presentation 1993/8/26
Ultra-high-Speed and Universal-coding-rate Viterbi Decoder VLSIC- SNUFEC VLSI-
Katsuhiko Kawazoe, Shunji Honda, Shuji Kubota, Shuzo Kato,
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Abstract(in English) An Ultra-high-speed(higher than 60MHz)Viterbi decoder VLSIC with coding rates from onehalf to fifteen-sixteenth and a constraint length of seven for forward error correction(FEC)has been developed using 0.8-mm semi-custom CMOS LSIC technology.To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder,a newly developed universal-coding-rate scarce- statetransition(SST)Viterbi decoding scheme and low-power- consumption burst-mode-selection(BMS)path memory have been employed.In addition,a new maximum-likelihood-decision(MLD)circuit for the SST Viterbi decoder has been developed to reduce the path memory length without any coding-gain degradation.The developed Viterbi decoder VLSIC achieves a maximum operation speed of 60MHz and achieves near theoretical net coding-gain performance for various coding rates.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Error correction / Convolutional codes / Viterbi Decoding / VLSI
Paper # SAT93-22,IN93-24,SST93-22
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Committee SAT
Conference Date 1993/8/26(1days)
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Registration To Satellite Telecommunications (SAT)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Ultra-high-Speed and Universal-coding-rate Viterbi Decoder VLSIC- SNUFEC VLSI-
Sub Title (in English)
Keyword(1) Error correction
Keyword(2) Convolutional codes
Keyword(3) Viterbi Decoding
Keyword(4) VLSI
1st Author's Name Katsuhiko Kawazoe
1st Author's Affiliation NTT()
2nd Author's Name Shunji Honda
2nd Author's Affiliation NTT
3rd Author's Name Shuji Kubota
3rd Author's Affiliation NTT
4th Author's Name Shuzo Kato
4th Author's Affiliation NTT
Date 1993/8/26
Paper # SAT93-22,IN93-24,SST93-22
Volume (vol) vol.93
Number (no) 193
Page pp.pp.-
#Pages 6
Date of Issue