Presentation 1996/7/23
A Triple Tuned PLL Frequency Synthesizer Driven by DDS and its Frequency Setting Algorithm for Low Spurious Characteristics
Ken'ichi TAJIMA, Kenji ITOH,
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Abstract(in English) A PLL frequency synthesizer driven by DDS achieves a narrow channel bandwidth without a degradation of the phase noise. This synthesizer is not employed commonly because of the high level of spurious components due to DDS. A triple tuned PLL frequency synthesizer driven by DDS is proposed to suppress the level of spurious components. In this report, low spurious characteristics of the proposed synthesizer are described by analytical and experimental approaches. The proposed synthesizer corrects the frequency setting parameters of DDS and 2 frequency dividers to put the spurious components of DDS away from passband of the PLL. A developed 700MHz-band PLL synthesizer with channel step less than 1Hz has a spurious level below -50dBc and a phase noise of -80dBc/Hz@10kHz offset. These measured values satisfy the INTELSAT EARTH STATIONS STABDARDS(IESS-308).
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Keyword(in English) Synthesizer / Phase locked loop / DDS / spurious components / Phase noise
Paper # SAT96-59,MW96-70
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Committee SAT
Conference Date 1996/7/23(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Triple Tuned PLL Frequency Synthesizer Driven by DDS and its Frequency Setting Algorithm for Low Spurious Characteristics
Sub Title (in English)
Keyword(1) Synthesizer
Keyword(2) Phase locked loop
Keyword(3) DDS
Keyword(4) spurious components
Keyword(5) Phase noise
1st Author's Name Ken'ichi TAJIMA
1st Author's Affiliation Mitsubishi Electric Corp.()
2nd Author's Name Kenji ITOH
2nd Author's Affiliation Mitsubishi Electric Corp.
Date 1996/7/23
Paper # SAT96-59,MW96-70
Volume (vol) vol.96
Number (no) 169
Page pp.pp.-
#Pages 8
Date of Issue