| Presentation | 2000/6/19 Implementing the Parallel Algorithms in the Multithreaded Architecture using High-Level Languadge TORU FURUTA, AKIHITO ITO, HIDEAKI KINOSITA, KOJI NAKANO, TATSUYA HAYASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Many parallel algorithms on the PRAM have been developed, so far. However, the PRAM is an unrealistic model of parallel computers, because it has a shared memory uniformily accessed by processors. The main contribution of this work is to develop a simulator and a compiler of the multithreaded architecture. For a given PRAM program written by a C-like language, this compiler generates a machine program executable on the simulator. To clarify the power of the multithreaded architecture, we executed several PRAM algorithms in it and evaluated their performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multithread architecture / PRAM algorithm / complier |
| Paper # | COMP2000-23 |
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| Conference Information | |
| Committee | COMP |
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| Conference Date | 2000/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Theoretical Foundations of Computing (COMP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementing the Parallel Algorithms in the Multithreaded Architecture using High-Level Languadge |
| Sub Title (in English) | |
| Keyword(1) | multithread architecture |
| Keyword(2) | PRAM algorithm |
| Keyword(3) | complier |
| 1st Author's Name | TORU FURUTA |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology() |
| 2nd Author's Name | AKIHITO ITO |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 3rd Author's Name | HIDEAKI KINOSITA |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 4th Author's Name | KOJI NAKANO |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 5th Author's Name | TATSUYA HAYASHI |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| Date | 2000/6/19 |
| Paper # | COMP2000-23 |
| Volume (vol) | vol.100 |
| Number (no) | 144 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |