Presentation	1998/5/29 Hardware Algorithm for Computing Euclidean Distance Seiji KUWAHARA, Naofumi TAKAGI,
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Abstract(in English)	A subtract-and-shift type hardware algorithm for computing Euclidean distance which is important in computer graphics is proposed. A combinational circuit for n-bit Euclidean distance computation based on the proposed algorithm has O(n)delay, O(n^2)size, O(n^2)area and a regular array structure suitable for VLSI implementation. A sequential circuit which executes one or a couple of steps per cycle has constant clock period, O(n)size, O(n)area and a regular liner array structure with bit-slice feature. O(n)clock cycles are required to perform n-bit Euclidean distance compitations.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	computer arithmetic / hardware algorithm / Euclidean dictance
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Conference Information
Committee	COMP
Conference Date	1998/5/29(1days)
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Paper Information
Registration To	Theoretical Foundations of Computing (COMP)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	Hardware Algorithm for Computing Euclidean Distance
Sub Title (in English)
Keyword(1)	computer arithmetic
Keyword(2)	hardware algorithm
Keyword(3)	Euclidean dictance
1st Author's Name	Seiji KUWAHARA
1st Author's Affiliation	Department of Information Engineering, Nagoya University.()
2nd Author's Name	Naofumi TAKAGI
2nd Author's Affiliation	Department of Information Engineering, Nagoya University.
Date	1998/5/29
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Volume (vol)	vol.98
Number (no)	93
Page	pp.pp.-
#Pages	8
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