Presentation 1996/1/26
A Hardware Algorithm for Right-Shift Modular Division with a Redundant Binary Representation
Kouichi Nakahara, Naofumi Takagi, Shuzo Yajima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A hardware algorithm for modular division is proposed. The binary gcd method is extended to perform modular division. Modular division is performed through iteration of simple operations, such as right-shifts and additions. The redundant binary representation with a digit set {0, 1, -1} is employed so that additions are performed without carry propagation. A modular division is carried out in O(n) clock cycles where n is the word length of the operands. The length of each clock cycle is constant independent of n. A modular divider based on the algorithm has a regular cellular array structure with a bit slice feature and is very suitable for VLSI implementation. Its amount of hardware is proportional to n.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) modular division / modular arithmetic / hardware algorithm / redundant binary / gcd
Paper # COMP95-76
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Conference Information
Committee COMP
Conference Date 1996/1/26(1days)
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Registration To Theoretical Foundations of Computing (COMP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hardware Algorithm for Right-Shift Modular Division with a Redundant Binary Representation
Sub Title (in English)
Keyword(1) modular division
Keyword(2) modular arithmetic
Keyword(3) hardware algorithm
Keyword(4) redundant binary
Keyword(5) gcd
1st Author's Name Kouichi Nakahara
1st Author's Affiliation Department of Information Science Kyoto University()
2nd Author's Name Naofumi Takagi
2nd Author's Affiliation Department of Information Engineering Nagoya University
3rd Author's Name Shuzo Yajima
3rd Author's Affiliation Department of Information Science Kyoto University
Date 1996/1/26
Paper # COMP95-76
Volume (vol) vol.95
Number (no) 498
Page pp.pp.-
#Pages 7
Date of Issue