| Presentation | 1995/4/21 Finding Minimal Deadlocks in General Petri Nets Shinji Tanimoto, Masahiro Yamauchi, Toshimasa Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A (structural) deadlock D of a Petri net is defined as a set of places such that the set of input transitions of D is included in the set of output ones of D. A minimal deadlock is a deadlocks such that any proper subset of D is not a deadlock. It is known that finding minimal deadlocks in a free-choice net, which is a subclass of Petri nets, can be solved in linear time. For general Petri nets, however, it does not seem that any efficient algorithm has ever been proposed. This paper proposes a polynomial time algorithm for finding a maximal class of pairwise disjoint minimal deadlocks of a given general Petri net. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | General Petri nets / Minimal Deadlocks / Polynomial Time Algorithms / Strongly Connected |
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| Conference Information | |
| Committee | COMP |
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| Conference Date | 1995/4/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Theoretical Foundations of Computing (COMP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Finding Minimal Deadlocks in General Petri Nets |
| Sub Title (in English) | |
| Keyword(1) | General Petri nets |
| Keyword(2) | Minimal Deadlocks |
| Keyword(3) | Polynomial Time Algorithms |
| Keyword(4) | Strongly Connected |
| 1st Author's Name | Shinji Tanimoto |
| 1st Author's Affiliation | Department of Circuits and Systems, Faculty of Engineering, Hiroshima University() |
| 2nd Author's Name | Masahiro Yamauchi |
| 2nd Author's Affiliation | Department of Circuits and Systems, Faculty of Engineering, Hiroshima University |
| 3rd Author's Name | Toshimasa Watanabe |
| 3rd Author's Affiliation | Department of Circuits and Systems, Faculty of Engineering, Hiroshima University |
| Date | 1995/4/21 |
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| Volume (vol) | vol.95 |
| Number (no) | 13 |
| Page | pp.pp.- |
| #Pages | 10 |
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