Presentation 1997/5/14
Development of a linear network model for prediction of malfunction of digital circuits
Naoki KAGAWA, Osami WADA, Ryuji KOGA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This report proposes a liner network model for prediction of malfunction of digital circuits. This model aims to simulate a CMOS digital IC under transient state. In this report, developed model simulates the simplest CMOS-IC, 74HCU04, which consists of a CMOS gate. Resonance of the model was calculated with SPICE and the results were compared with the measured frequency characteristics of wide band noise voltage overriding digital signals. As a result, the model simulated a peak frequency where the noise voltage has maximal value.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digital circuit / malfunction / equivalent circuit / resonance characteristics / CMOS logic IC
Paper # EMCJ97-13
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Conference Information
Committee EMCJ
Conference Date 1997/5/14(1days)
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Registration To Electromagnetic Compatibility (EMCJ)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of a linear network model for prediction of malfunction of digital circuits
Sub Title (in English)
Keyword(1) Digital circuit
Keyword(2) malfunction
Keyword(3) equivalent circuit
Keyword(4) resonance characteristics
Keyword(5) CMOS logic IC
1st Author's Name Naoki KAGAWA
1st Author's Affiliation Faculty of Engineering, Fukuyama University()
2nd Author's Name Osami WADA
2nd Author's Affiliation Faculty of Engineering, Okayama University
3rd Author's Name Ryuji KOGA
3rd Author's Affiliation Faculty of Engineering, Okayama University
Date 1997/5/14
Paper # EMCJ97-13
Volume (vol) vol.97
Number (no) 37
Page pp.pp.-
#Pages 6
Date of Issue