| Presentation | 2000/11/10 Hot Carrier Degradation of p^+ Polysilicon Gated pMOSFETs M. Fujimoto, T. Nakajima, S. Nakano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Through the investigation of the hot carrier degradation of p^+ polysilicon gated pMOSFETs at three kinds of stress condition, which are Igmax, Isubmax and CHC stress, the following mechanism was found. At Igmax stress condition, Ids and gm increase due to the drain avalanche hot electron injection. At Isubmax stress condition, Ids and gm increase due to the drain avalanche hot electron injection at the first time and decrease due to the drain avalanche hot hole injection. At CHC stress condition, Ids and gm decrease due to the channel hot hole injection. From these results, there are three hot carrier degradation of pMOSFETs. The relationship between the hot carrier lifetime and the stress voltage is different at three stress conditions. So It is necessary to study the stress voltage dependence of hot carrier lifetime at all stress condit ion to predict the accurate hot carrier lifetime. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hot carrier / pMOSFETs / p^+ Polysilicon gate |
| Paper # | R2000-23 |
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| Conference Information | |
| Committee | R |
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| Conference Date | 2000/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reliability(R) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hot Carrier Degradation of p^+ Polysilicon Gated pMOSFETs |
| Sub Title (in English) | |
| Keyword(1) | hot carrier |
| Keyword(2) | pMOSFETs |
| Keyword(3) | p^+ Polysilicon gate |
| 1st Author's Name | M. Fujimoto |
| 1st Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation() |
| 2nd Author's Name | T. Nakajima |
| 2nd Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation |
| 3rd Author's Name | S. Nakano |
| 3rd Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation |
| Date | 2000/11/10 |
| Paper # | R2000-23 |
| Volume (vol) | vol.100 |
| Number (no) | 445 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |