| Presentation | 2000/11/10 Positive Bias Temperature Instability of p^+ Polysilicon Gated pMOSFETs Tadayuki Nakajima, Masahiro Fujimoto, Shinji Nakano, Ichiro Matsuo, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We studied for the degradation of p^+ polysilicon gated pMOSFETs under positive bias temperature (+BT) stress and the recovery by the baking. The following facts were found. 1.Under+BT stress, the p^+ polysilicon gated pMOSFETs was degraded by the interface trap generation. This phenomenon does not occur in the n^+ polysilicon gated pMOSFETs. The silicon-hydrogen bonds at the Si/SiO_2 become the interface traps by the influence of the hydrogen. 2.The interface traps which generated under +BT stress recover easily by the baking. We consider that this recovery is the influence of the hydrogen, too. 3.The activation energy of the +BT instability and the recovery were 1.2eV and 1.0eV, respectively. This difference 0.2eV is the energy gap between the silicon-hydrogen bonds and the interface state. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Bias temperature instability / interface trap / pMOSFET |
| Paper # | R2000-22 |
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| Conference Information | |
| Committee | R |
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| Conference Date | 2000/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reliability(R) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Positive Bias Temperature Instability of p^+ Polysilicon Gated pMOSFETs |
| Sub Title (in English) | |
| Keyword(1) | Bias temperature instability |
| Keyword(2) | interface trap |
| Keyword(3) | pMOSFET |
| 1st Author's Name | Tadayuki Nakajima |
| 1st Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation() |
| 2nd Author's Name | Masahiro Fujimoto |
| 2nd Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation |
| 3rd Author's Name | Shinji Nakano |
| 3rd Author's Affiliation | Quality Laboratory, Semiconductor Company, Matsushita Electronics Corporation |
| 4th Author's Name | Ichiro Matsuo |
| 4th Author's Affiliation | ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corporation |
| Date | 2000/11/10 |
| Paper # | R2000-22 |
| Volume (vol) | vol.100 |
| Number (no) | 445 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |