| Presentation | 1995/11/10 Development of high density package by stacking IC chips Katsunobu Mori, Hiroyuki Nakanishi, Atsuya Narai, Toshiya Ishio, Satoru Fukunaga, kazuya Fujita, Morihiro Kada, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Stacked Chips Package containing two IC chips in it has been developed. Most of the conventional packaging materials can be used for this technology and the existing production equipments can also be utilized without making assembly process more complicated. This package structure employs to mount each IC chip onto the both sides of a die pad. Having such structure, normally the passivation layer on the surface of the IC chip is easily damaged during the production. However, such problem has been overcome by forming a protective coating on the surface of the IC chip and attaching the stress absorbing material on the jig which is in contact with the surface the chip. The same reliability level as convetional IC package has been achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Stacking IC chip / High density Package / Protective coating on the surface / Stress absorbing material |
| Paper # | R95-20 |
| Date of Issue |
| Conference Information | |
| Committee | R |
|---|---|
| Conference Date | 1995/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reliability(R) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of high density package by stacking IC chips |
| Sub Title (in English) | |
| Keyword(1) | Stacking IC chip |
| Keyword(2) | High density Package |
| Keyword(3) | Protective coating on the surface |
| Keyword(4) | Stress absorbing material |
| 1st Author's Name | Katsunobu Mori |
| 1st Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation() |
| 2nd Author's Name | Hiroyuki Nakanishi |
| 2nd Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| 3rd Author's Name | Atsuya Narai |
| 3rd Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| 4th Author's Name | Toshiya Ishio |
| 4th Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| 5th Author's Name | Satoru Fukunaga |
| 5th Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| 6th Author's Name | kazuya Fujita |
| 6th Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| 7th Author's Name | Morihiro Kada |
| 7th Author's Affiliation | Production Engineering Dept. VLSI Development Laboratories Tenri Integrated Circuits Group, Sharp Corporation |
| Date | 1995/11/10 |
| Paper # | R95-20 |
| Volume (vol) | vol.95 |
| Number (no) | 348 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |