Presentation 1998/3/13
High Accuracy Backside Emission Microscopy in a LSI Chip by CAD Layout Pattern Overlay
Tatsuya Ishii, Koji Azamawari, Norio Asatani, Jun-ichi Mitsuhashi,
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Abstract(in English) In the backside emission microscopy for failure analysis of LSIs with the multi-level metallization process, flip-chip technology and CSP/LOC package, decrease of chip image contrast and/or resolution becomes the recognizing of photo emission site more difficult. CAD layout pattern overlay technique has been developed for high accurate recognition of photo emitting point. The quarter micron level accuracy of recognizing emitting site has been achieved by three point alignment method on the software. We show this technique is effective for actual failure analysis using advanced DRAM application.
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Keyword(in English) silicon LSI / failure analysis / emission microscopy / fault isolation / CAD linkage
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Conference Date 1998/3/13(1days)
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Title (in English) High Accuracy Backside Emission Microscopy in a LSI Chip by CAD Layout Pattern Overlay
Sub Title (in English)
Keyword(1) silicon LSI
Keyword(2) failure analysis
Keyword(3) emission microscopy
Keyword(4) fault isolation
Keyword(5) CAD linkage
1st Author's Name Tatsuya Ishii
1st Author's Affiliation Semiconductor Group Manufacturing Technology Div.Mitsubishi Electric Corp.()
2nd Author's Name Koji Azamawari
2nd Author's Affiliation Semiconductor Works Tada Eiectric Corp.
3rd Author's Name Norio Asatani
3rd Author's Affiliation Semiconductor Group Manufacturing Technology Div.Mitsubishi Electric Corp.
4th Author's Name Jun-ichi Mitsuhashi
4th Author's Affiliation Semiconductor Group Manufacturing Technology Div.Mitsubishi Electric Corp.
Date 1998/3/13
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Volume (vol) vol.97
Number (no) 600
Page pp.pp.-
#Pages 6
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