Presentation 2002/9/20
A Calibration Method for High-Frequency PLL Synthesizer
Yoshiyuki SHIBAHARA, Masaru KOKUBO,
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Abstract(in English) This paper presents a calibration method for a high-frequency PLL synthesizer. As the frequency of the PLL synthesizer becomes high, a voltage-to-frequency conversion gain of a voltage-controlled oscillator (VCO) must be increased and PLL become sensitive to noise. The voltage-to-frequency conversion gain can be reduced by applying constant bias current to VCO and making the VCO minimum frequency offset from the zero frequency. In the conventional method, however, according to the large device variation of CMOS process, it is difficult to satisfy the desired frequency range and PLL might fail to lock. In our work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band. Simulation result shows that the voltage-to-frequency conversion gain is reduced to 25% of the conventional VCO.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PLL / Calibration / VCO / Low Voltage
Paper # ICD2002-99
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Conference Date 2002/9/20(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Calibration Method for High-Frequency PLL Synthesizer
Sub Title (in English)
Keyword(1) PLL
Keyword(2) Calibration
Keyword(3) VCO
Keyword(4) Low Voltage
1st Author's Name Yoshiyuki SHIBAHARA
1st Author's Affiliation Central Research Laboratory, Hitachi Ltd()
2nd Author's Name Masaru KOKUBO
2nd Author's Affiliation Central Research Laboratory, Hitachi Ltd
Date 2002/9/20
Paper # ICD2002-99
Volume (vol) vol.102
Number (no) 340
Page pp.pp.-
#Pages 5
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