Presentation 2002/9/20
A CMOS PLL Clock Generator Using a Source-Voltage Controlled Oscillator (S-VCO)
Tomochika HARADA, Tadayoshi ENOMOTO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A source voltage-controlled oscillator (S-VCO), whose oscillating frequency f is controlled by a source voltage of MOSFET, has been developed. A phase-locked-loop (PLL) clock generator incorporating the S-VCO was fabricated by using 0.6μm 2-poly 3-metal CMOS technology The number of MOSFETs in the S-VCO is about 1/2 that in a conventional current-starved VCO. The voltage sensitivity of a fabricated 43-stage S-VCO with a single 3.3-V power supply (V_D) is approximately 70.3 MHZ/V. At 50.0 MHz oscillation and 3.3V power supply, the measured jitter was 418 psec (2.09 %).
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Voltage-Controlled Oscillator / Source Voltage / S-VCO / Phase Locked Loop / jitter / CMOS
Paper # ICD2002-98
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Committee ICD
Conference Date 2002/9/20(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A CMOS PLL Clock Generator Using a Source-Voltage Controlled Oscillator (S-VCO)
Sub Title (in English)
Keyword(1) Voltage-Controlled Oscillator
Keyword(2) Source Voltage
Keyword(3) S-VCO
Keyword(4) Phase Locked Loop
Keyword(5) jitter
Keyword(6) CMOS
1st Author's Name Tomochika HARADA
1st Author's Affiliation Faculty of Science and Engineering, Chuo University()
2nd Author's Name Tadayoshi ENOMOTO
2nd Author's Affiliation Faculty of Science and Engineering, Chuo University
Date 2002/9/20
Paper # ICD2002-98
Volume (vol) vol.102
Number (no) 340
Page pp.pp.-
#Pages 6
Date of Issue