| Presentation | 2002/2/28 Technology Trend of IP-Reuse on System LSI Design Tadahiko Nakamura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | IP Reuse-based design methodology has been devised to improve design productivity in SoC designs, but the applied range of IP Reuse is limited. IP-data required has so wide varieties, and deeply depend on the process technology and design environment for semiconductor companies. It is very difficult for IP-User to select the best IP before starting the SoC design procedure. The STARC IP-based design technology set is the solution for these difficulties. The set includes (1) technical infrastructures such as the design style guide and IP trading standard, (2) common design rules of 2D geometries and SPICE parameters, (3) IP libraries. STRAC and its twelve member companies agreed to promote the technology set throughout the SoC industry to make IP trade and reuse much more efficient among the adopting companies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC / IP / reuse / 2D geometries / SPICE parameters / delivery / Silicon proven IP |
| Paper # | ICD2001-234 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Technology Trend of IP-Reuse on System LSI Design |
| Sub Title (in English) | |
| Keyword(1) | SoC |
| Keyword(2) | IP |
| Keyword(3) | reuse |
| Keyword(4) | 2D geometries |
| Keyword(5) | SPICE parameters |
| Keyword(6) | delivery |
| Keyword(7) | Silicon proven IP |
| 1st Author's Name | Tadahiko Nakamura |
| 1st Author's Affiliation | Semiconductor Technology Academic Research Center (STARC)() |
| Date | 2002/2/28 |
| Paper # | ICD2001-234 |
| Volume (vol) | vol.101 |
| Number (no) | 696 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |