Presentation 2001/12/14
A Shared Built-In Self-Repair Analysis for Multiple Embedded Memories
Masanao MARUTA, Jun OHTANI, Tomoya KAWAGOE, Mitsutaka NIIRO, Tukasa OOISHI, Mitsuhiro HAMADA, Hideto HIDAKA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A Shared Built-In Self-Repair Analysis scheme(Shared-BISA)for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compactre-configurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500MHz.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BISA / CRESTA / Redundancy / Test / Repair algorithm / embedded Memory / Realtime Analysis
Paper # CPM-126,ICD-178
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Conference Date 2001/12/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Shared Built-In Self-Repair Analysis for Multiple Embedded Memories
Sub Title (in English)
Keyword(1) BISA
Keyword(2) CRESTA
Keyword(3) Redundancy
Keyword(4) Test
Keyword(5) Repair algorithm
Keyword(6) embedded Memory
Keyword(7) Realtime Analysis
1st Author's Name Masanao MARUTA
1st Author's Affiliation ULSI Development Center()
2nd Author's Name Jun OHTANI
2nd Author's Affiliation ULSI Development Center
3rd Author's Name Tomoya KAWAGOE
3rd Author's Affiliation ULSI Development Center
4th Author's Name Mitsutaka NIIRO
4th Author's Affiliation ULSI Development Center
5th Author's Name Tukasa OOISHI
5th Author's Affiliation ULSI Development Center
6th Author's Name Mitsuhiro HAMADA
6th Author's Affiliation Manufacturing Technology & Production Management Div., Mitsubishi Electric Corp.
7th Author's Name Hideto HIDAKA
7th Author's Affiliation ULSI Development Center
Date 2001/12/14
Paper # CPM-126,ICD-178
Volume (vol) vol.101
Number (no) 519
Page pp.pp.-
#Pages 7
Date of Issue