| Presentation | 2001/11/30 Modeling of Power Consumption for Super-cell Based on Statically Substrate-biased Domino CMOS Circuit Toshiro Akino, Makoto Nagata, Takanori Yoshiyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a circuit scheme making the most of pull-up/pull-down transistors with high threshold voltages by static substrate-biases. Here, the source terminals of these transistors were only connected to the base of power supply and ground. We reduced the area of domino CMOS circuits only with NMOS having a low threshold voltage and without its PMOS[1, 2, 3]. Furthermore, in order to achieve a quick timing closure, we proposed the layout architecture of super-cell of the domino CMOS circuits with continuously variable transistor width which can correspond to the output load of interconnection RC[4, 5, 6]. Also, we improved the above layout architecture for AO23(2-input AND/3-paralallel OR)as a typical cell and re-established the delay model[7]In this paper, we investigate a power consumption model for the super-cell to three independent measures of transistor width, interconnection RC, and fanout capacitance, using a circuit simulator based on the BSIM3v3 model of 0.35μm CMOS process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | substrate-bias / threshold voltage / domino CMOS circuit / timing closure / super-cell |
| Paper # | VLD2001-112,ICD2001-157,FTS2001-59 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/11/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Modeling of Power Consumption for Super-cell Based on Statically Substrate-biased Domino CMOS Circuit |
| Sub Title (in English) | |
| Keyword(1) | substrate-bias |
| Keyword(2) | threshold voltage |
| Keyword(3) | domino CMOS circuit |
| Keyword(4) | timing closure |
| Keyword(5) | super-cell |
| 1st Author's Name | Toshiro Akino |
| 1st Author's Affiliation | Department of Electronic System and Information Engineering, School of Biology-Oriented Science and Technology, Kinki University() |
| 2nd Author's Name | Makoto Nagata |
| 2nd Author's Affiliation | Department of Electronic System and Information Engineering, School of Biology-Oriented Science and Technology, Kinki University |
| 3rd Author's Name | Takanori Yoshiyama |
| 3rd Author's Affiliation | Department of Electronic System and Information Engineering, School of Biology-Oriented Science and Technology, Kinki University |
| Date | 2001/11/30 |
| Paper # | VLD2001-112,ICD2001-157,FTS2001-59 |
| Volume (vol) | vol.101 |
| Number (no) | 471 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |