Presentation | 2001/11/29 Physical Design Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor Rei AKIYAMA, Hidehiro TAKATA, Tadao YAMANAKA, Haruyuki OHKUMA, Yasue SUETSUGU, Toshihiro KANAOKA, Satoshi KUMAKI, Kazuya ISHIHARA, Atsuo HANAMI, Tetsuya MATSUMURA, Tetsuya WATANABE, Yoshihide AJIOKA, Yoshio MATSUDA, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | An on-chip, 64-Mb, embedded, DRAM MPEG-2 encoder LSI with a multimedia processor has been developed. To implement this large-scale and high-speed LSI, we have developed the hierarchical skew control of multi-clocks, with timing verification, in which cross-talk noise is considered, and simple measures taken against the IR drop in the power lines through decoupling capacitors. As a result, the target performance of 263 MHz at 1.5 V has been successfully attained and verified, the cross-talk noise has been considered, and, in addition, it has become possible to restrain the IR drop to 166 mV in the 162 MHz operation block. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Multimedia processor / Clock skew / Cross-talk noise / IR drop / Video encoder / MPEG-2 |
Paper # | VLD2001-94,ICD2001-139,FTS2001-41 |
Date of Issue |
Conference Information | |
Committee | ICD |
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Conference Date | 2001/11/29(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Physical Design Methodology for On-chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor |
Sub Title (in English) | |
Keyword(1) | Multimedia processor |
Keyword(2) | Clock skew |
Keyword(3) | Cross-talk noise |
Keyword(4) | IR drop |
Keyword(5) | Video encoder |
Keyword(6) | MPEG-2 |
1st Author's Name | Rei AKIYAMA |
1st Author's Affiliation | Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation() |
2nd Author's Name | Hidehiro TAKATA |
2nd Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
3rd Author's Name | Tadao YAMANAKA |
3rd Author's Affiliation | Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation |
4th Author's Name | Haruyuki OHKUMA |
4th Author's Affiliation | Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation |
5th Author's Name | Yasue SUETSUGU |
5th Author's Affiliation | Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation |
6th Author's Name | Toshihiro KANAOKA |
6th Author's Affiliation | Electronic Devices Design Center, Mitsubishi Electric Engineering Corporation |
7th Author's Name | Satoshi KUMAKI |
7th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
8th Author's Name | Kazuya ISHIHARA |
8th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
9th Author's Name | Atsuo HANAMI |
9th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
10th Author's Name | Tetsuya MATSUMURA |
10th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
11th Author's Name | Tetsuya WATANABE |
11th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
12th Author's Name | Yoshihide AJIOKA |
12th Author's Affiliation | System LSI Division, Mitsubishi Electric Corporation |
13th Author's Name | Yoshio MATSUDA |
13th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
Date | 2001/11/29 |
Paper # | VLD2001-94,ICD2001-139,FTS2001-41 |
Volume (vol) | vol.101 |
Number (no) | 470 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |