Presentation	2001/8/31 Evaluation Results of a 0.7V-200MHz self-calibration PLL Yoshiyuki SHIBAHARA, Masaru KOKUBO,
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Abstract(in English)	This paper presents evaluation results of sub 1V Phase Locked Loop(PLL).By means of large leakage current of the deep sub-micron CMOS.the minimum oscillation frequecy of a voltage controlled oscillator exceeds the desired tuning range and the PLL fails to lock.In this work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band.The prtotype PLL demonstrates a settling time of 10μs, a cycle-to-cycle jitter of 142ps, and a power consumption of 470μW at 0.7V-200MHz.Moreover, the maximum operating frequency of the PLL is as high as 400MHz at 0.7V.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Low Voltage / Low Threshold Voltage Transistor / Leakage current / PLL / Calibration
Paper #	ICD2001-95
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Committee	ICD
Conference Date	2001/8/31(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Evaluation Results of a 0.7V-200MHz self-calibration PLL
Sub Title (in English)
Keyword(1)	Low Voltage
Keyword(2)	Low Threshold Voltage Transistor
Keyword(3)	Leakage current
Keyword(4)	PLL
Keyword(5)	Calibration
1st Author's Name	Yoshiyuki SHIBAHARA
1st Author's Affiliation	Central Research Laboatory, Hitachi Ltd()
2nd Author's Name	Masaru KOKUBO
2nd Author's Affiliation	Central Research Laboatory, Hitachi Ltd
Date	2001/8/31
Paper #	ICD2001-95
Volume (vol)	vol.101
Number (no)	282
Page	pp.pp.-
#Pages	6
Date of Issue