| Presentation | 2001/7/27 Low Resistivity TaNx/Ta/TaNx Metal Gate Si_3N_4-MNS Technology Featuring Low-Temperature Processing Ichiro Ohshima, Hiroyuki Shimada, Shin-ichi Nakao, Weitao Cheng, Yasuhiro Ono, Masaki Hirayama, Shigetoshi Sugawa, Tadahiro Ohmi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor(MNS)FET technology having conventional plane gate structure featuring fully low-temperature processing.The gate stack consists of directly grown Silicon Nitride(Si_3N_4)dielectric using high-density plasma and bcc-phase Tantalum(～15μΩcm)/Tantalum Nitride(bcc-Ta/TaNx)stacked metal gate below 1.0ohm/sq.In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy(SPE)method.In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric(FDSOI)metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Si_3N_4 / High Density Plasma / Low Temperature Processing / Metal Gate / Tantalum / TaNx |
| Paper # | SDM2001-139,ICD2001-62 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/7/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low Resistivity TaNx/Ta/TaNx Metal Gate Si_3N_4-MNS Technology Featuring Low-Temperature Processing |
| Sub Title (in English) | |
| Keyword(1) | Si_3N_4 |
| Keyword(2) | High Density Plasma |
| Keyword(3) | Low Temperature Processing |
| Keyword(4) | Metal Gate |
| Keyword(5) | Tantalum |
| Keyword(6) | TaNx |
| 1st Author's Name | Ichiro Ohshima |
| 1st Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University() |
| 2nd Author's Name | Hiroyuki Shimada |
| 2nd Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University:SEIKO EPSON Corporation |
| 3rd Author's Name | Shin-ichi Nakao |
| 3rd Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University |
| 4th Author's Name | Weitao Cheng |
| 4th Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University |
| 5th Author's Name | Yasuhiro Ono |
| 5th Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University:SEIKO EPSON Corporation |
| 6th Author's Name | Masaki Hirayama |
| 6th Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University |
| 7th Author's Name | Shigetoshi Sugawa |
| 7th Author's Affiliation | Department of Electronic Engineering, Graduate School of Engineering, Tohoku University |
| 8th Author's Name | Tadahiro Ohmi |
| 8th Author's Affiliation | New Industry Creation Hatchery Center, Tohoku University |
| Date | 2001/7/27 |
| Paper # | SDM2001-139,ICD2001-62 |
| Volume (vol) | vol.101 |
| Number (no) | 249 |
| Page | pp.pp.- |
| #Pages | 6 |
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