Presentation 2001/7/27
A Threshold Logic-Based High-Speed Hamming Distance Detector and its Evaluation
Hiroaki YAMAOKA, Kunihiro ASADA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper proposes a high-speed Hamming distance detector using a threshold logic circuit.The proposed circuit accepts two bit-streams and is capable of detecting if the two bit-streams are identical, and if the Hamming distance between the two bit-streams is within a certain range or a specified value, while the conventional Hamming distance detectors such as CAMs(Content Addressable Memories)detect if the two bit-streams are identical, or if the Hamming distance between the two bit-streams is minimum.The configuration of a CAM with the proposed circuit and simulation results of robustness for process variations are also shown.
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Keyword(in English) high-speed CMOS circuit / threshold logic / Hamming distance / CAM
Paper # SDM2001-134,ICD2001-57
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Conference Date 2001/7/27(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Threshold Logic-Based High-Speed Hamming Distance Detector and its Evaluation
Sub Title (in English)
Keyword(1) high-speed CMOS circuit
Keyword(2) threshold logic
Keyword(3) Hamming distance
Keyword(4) CAM
1st Author's Name Hiroaki YAMAOKA
1st Author's Affiliation Department of Electronics Engineering, the University of Tokyo()
2nd Author's Name Kunihiro ASADA
2nd Author's Affiliation Department of Electronics Engineering, the University of Tokyo
Date 2001/7/27
Paper # SDM2001-134,ICD2001-57
Volume (vol) vol.101
Number (no) 249
Page pp.pp.-
#Pages 6
Date of Issue