| Presentation | 2001/7/26 High-Performance CMOS Circuits in Sub-100-nm Era : Issues and Solutions Kazuo Yano, Naoki Kato, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The changes of high-performance CMOS circuits in sub-100-nm era are studied. Currently simple static CMOSs, which are complemented by partial dynamic CMOS circuits, are used, however, this configuration should drastically be changed. The change driver is the tradeoff between active leakage and performance in sub-1-V region, which introduces the wide use of selective multiple-threshold-voltage design, which we call random-modulation CMOS, as a key circuit technology. Here, careful assignment of the threshold voltage in cell-by-cell manner based on precise static timing analysis is essential. Another important aspect of sub-1-V region is that the benefits of dynamic circuits are eroded, which drives the pursuit of high-performance design in static circuits. Taking these changes as the first step, the era of "complex CMOS, " which requires complicated design elaborations and operating control, begins. Another new direction is the moderate low-temperature operation, e.g.at 0 degree C, might be more widely used five years from now than what is currently perceived. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-performance CMOS / sub-100-nm / leakage / supply voltage / low-temperature operation |
| Paper # | SDM2001-120,ICD2001-43 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Performance CMOS Circuits in Sub-100-nm Era : Issues and Solutions |
| Sub Title (in English) | |
| Keyword(1) | high-performance CMOS |
| Keyword(2) | sub-100-nm |
| Keyword(3) | leakage |
| Keyword(4) | supply voltage |
| Keyword(5) | low-temperature operation |
| 1st Author's Name | Kazuo Yano |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi Ltd.() |
| 2nd Author's Name | Naoki Kato |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi Ltd. |
| Date | 2001/7/26 |
| Paper # | SDM2001-120,ICD2001-43 |
| Volume (vol) | vol.101 |
| Number (no) | 248 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |