Presentation 2001/5/18
Interface Socket Design Methodology to Generate Embedded DRAM Macros
Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Hiroyuki Takenaka, Takehiko Hojo,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18um technology.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) embedded DRAM / interface / RTL / design flow / verification
Paper # ICD2001-35
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Conference Date 2001/5/18(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Interface Socket Design Methodology to Generate Embedded DRAM Macros
Sub Title (in English)
Keyword(1) embedded DRAM
Keyword(2) interface
Keyword(3) RTL
Keyword(4) design flow
Keyword(5) verification
1st Author's Name Ryo Haga
1st Author's Affiliation Toshiba Colporation()
2nd Author's Name Tetsuya Kaneko
2nd Author's Affiliation Toshiba Colporation
3rd Author's Name Atsushi Nakayama
3rd Author's Affiliation Toshiba Colporation
4th Author's Name Hiroyuki Takenaka
4th Author's Affiliation Toshiba Colporation
5th Author's Name Takehiko Hojo
5th Author's Affiliation Toshiba Microelectronics Corporation
Date 2001/5/18
Paper # ICD2001-35
Volume (vol) vol.101
Number (no) 85
Page pp.pp.-
#Pages 7
Date of Issue