| Presentation | 2001/5/18 Utilizing Surplus Timing for Power Reduction Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Multiple supply voltage (Vdd), multiple threshold voltage (Vth), and multiple transistor width (W) for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Supply Voltage / Threshold Voltage / Optimum Value |
| Paper # | ICD2001-34 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2001/5/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Utilizing Surplus Timing for Power Reduction |
| Sub Title (in English) | |
| Keyword(1) | Supply Voltage |
| Keyword(2) | Threshold Voltage |
| Keyword(3) | Optimum Value |
| 1st Author's Name | Mototsugu Hamada |
| 1st Author's Affiliation | Toshiba Corp.() |
| 2nd Author's Name | Yukio Ootaguro |
| 2nd Author's Affiliation | Toshiba Corp. |
| 3rd Author's Name | Tadahiro Kuroda |
| 3rd Author's Affiliation | Keio University |
| Date | 2001/5/18 |
| Paper # | ICD2001-34 |
| Volume (vol) | vol.101 |
| Number (no) | 85 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |