Presentation 2001/5/18
V_
-hopping Scheme in Low-Voltage and Low-power Processors
Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai,
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Abstract(in English) A threshold voltage hopping (V_-hopping) scheme is proposed where V_ is dynamically controlled through software depending on a workload. V_-hopping is shown to reduce the power to 18% of the fixed low-V_ circuits in 0.5V supply voltage regime for multimedia applications. A positive back-gate bias scheme within V_-hopping is presented for the high-performance and low-voltage processors. The measurement result shows about 90% power reduction is possible by using V_-hopping.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low-power / Low-voltage / real-time application / positive back-bias
Paper # ICD2001-33
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Committee ICD
Conference Date 2001/5/18(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) V_-hopping Scheme in Low-Voltage and Low-power Processors
Sub Title (in English)
Keyword(1) Low-power
Keyword(2) Low-voltage
Keyword(3) real-time application
Keyword(4) positive back-bias
1st Author's Name Koichi Nose
1st Author's Affiliation Institute of Industrial Science, University of Tokyo()
2nd Author's Name Masayuki Hirabayashi
2nd Author's Affiliation Institute of Industrial Science, University of Tokyo
3rd Author's Name Hiroshi Kawaguchi
3rd Author's Affiliation Institute of Industrial Science, University of Tokyo
4th Author's Name Seongsoo Lee
4th Author's Affiliation Department of Information Electronics, Ewha University
5th Author's Name Takayasu Sakurai
5th Author's Affiliation Institute of Industrial Science, University of Tokyo
Date 2001/5/18
Paper # ICD2001-33
Volume (vol) vol.101
Number (no) 85
Page pp.pp.-
#Pages 7
Date of Issue